Member for
5 months
Role
Low Power ASIC Design
Points
10
SoC Labs Roles
Registered User

Projects

Articles

Design Flow

Technology

Authored Comments

Subject Comment Link to Comment
Thanks John.  My expertise…

Thanks John.  My expertise and interest are primarily on the low power design side (power control system architecture, clock/power gating/ reset design/DVFS control etc) and I am looking to be involved in the architecture and RTL design stage.  But I understand that they heavily use ARM components. Let me know If some related projected opens up in the future (if not an exact match to my interest/expertise) 

view

User statistics

My contributions
:
0
My comments
:
1

Comments

Hi,

I am very sorry for missing the message you sent to us. You don't have to be a student at an academic organisation to collaborate on a project but under the Arm AAA agreement you will not be able to access any Arm IP. It would be good to understand what you want to acheive and see if we can connect you to a project. There is a project on memory controller that is open to non-academics.

High Capacity Memory Subsystem Development | SoC Labs

John.

 

Thanks John.  My expertise and interest are primarily on the low power design side (power control system architecture, clock/power gating/ reset design/DVFS control etc) and I am looking to be involved in the architecture and RTL design stage.  But I understand that they heavily use ARM components. Let me know If some related projected opens up in the future (if not an exact match to my interest/expertise) 

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.