The dynamic range processor is a DSP function which does as it says on the tin; it compresses the dynamic range of the incoming signal. This is used most commonly in the music industry for its effects on the perceived loudness of audio. It is also used extensively in hearing aids to compensate for the user’s reduced dynamic range of hearing. In this project a hardware accelerator is developed for the purpose of dynamic range compression of digital audio. This accelerator will be implemented in a mixed-signal infrastructure.

The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC.  This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.

Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. This project is aimed at developing the necessary resources and design flow stages for the verification of the NanoSoC reference design.

With NanoSoC, there are multiple options for performing system-level verification. 

The k-Nearest-Neighbours (kNN) algorithm is a popular Machine Learning technique that can be used for a variety of supervised classification tasks. In contrast to other machine learning algorithms which "encode" the knowledge gained from training data to a set of parameters, such as weights and biases, the parameter set of a kNN classifier consists of just labelled training examples. Classification of an unlabelled example takes place by calculating its Euclidean distance (or any other type of distance metric) from all the stored training examples.